Dylan PatelFounder and Chief Analyst, SemiAnalysis · The semiconductor-AI stack

sram scaling is dead. going to smaller nanometer nodes doesn't solve the memory capacity problem any

27 May 2026 · 2 min

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Dylan Patel discusses why shrinking to smaller chip nodes no longer solves memory capacity problems. SRAM scaling has stalled despite Moore's Law, and moving from N5 to N3 provides minimal gains. The conversation covers alternatives like 3D SRAM and 3D DRAM, which offer much higher bit density than traditional approaches.

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Although Moore's Law has slowed down, but I think one of the big things is that SRAM scaling is dead. And then a lot of the area on a wafer-scale engine is SRAM, so 50%. So that means that just going to the next node, say from N5 to N3, a lot of, they just lose a lot of the benefits. Yeah. And it's pretty hard for them to increase on-chip memory capacity because of this.
Yeah, that's true. In the investor roadshow, they did disclose that their next generation system, CS4, will use the exact same WSE3 wafer, which is on 5nm. So clearly they agree as well, right? If not, they would have also jumped to the 3nm bandwagon. But they did mention other ways of increasing the amount of memory, which is to do with the area efficiency. So if I can get my compute with a new node, if I can get my compute area down, I have more room to place my SRAM. So that's one way to increase SRAM by maybe like 20-30%. And then on top of that, you have these scaling factors such as the vertical SRAM, like AMD's 3D cache. Or even the future 3D DRAM, right, which is like 10 to 15 times the bit density per area of SRAM. So these are some of the more difficult ways, but still ways to achieve this scaling.