Dylan PatelFounder and Chief Analyst, SemiAnalysis · The semiconductor-AI stack

Battle of the Scale Up: UALink vs SUE🔥🔥

22 Aug 2025 · 1 min

Watch on YouTube

0:47

This content was created by Dylan Patel. This content was uploaded by Dylan Patel. This is an excerpt from a YouTube video titled "Battle of the Scale Up: UALink vs SUE🔥🔥" (created 2025-08-22). It captures a short multi-speaker exchange (labeled SPEAKER A and SPEAKER B) in a debate/discussion format about hardware interface standards and latency — noting that Ethernet standards don't specify latencies while PCIe/CXL and related standards do — and references CXL and PCIe in the context of scale-up performance and workflows.

Standards do not specify latencies for Ethernet.
Really? Because in my PCI spec, it specifies latency. Why the PCI is exactly the PCIe has been. I mean, you look at CXL, PCIe, others, they all specify latencies in their standards.
That's why they've been talking about CXL for the last 5 years. I hope you guys have been successful with it.
So I don't know why a standard can't specify latency because they are rich standards.
They are rich standards.
And so that's what you need because the workflows, the models, the way they're performing. All right, so I'm going to interject here. So I finally get to do my job.