Ep. 040 - ASML Is Building a Hybrid Bonding Tool, and We Have the Patents (AI Supply Chain)

Travel back to Portland to tear down this phone. We brought one sample back to Singapore for testing.

What do you mean? You're going to plug it in in Singapore?

Yeah. And do benchmarks. Yeah. This Huawei phone. Yeah. It opens up.

Are you then going to plug a SIM card in it and do some qualitative testing as well?

Yeah, maybe. After that, we might sell it. Or if the teardown team needs another sample in case anything goes wrong, this is a backup.

You keep the backup teardown in your back pocket? Hello everyone. Welcome back to Semi Analysis Weekly. This is Jordan. I'm here with Howie and Sherry, and in this episode we're gonna be talking through an article that we just put out called ASML is Building a Hybrid Bonding Tool. Big news. It's not been announced yet, but we've got the patent filings, we've made some annotations, and we're gonna talk to the experts. So guys, welcome to the show. Excited for this one.

Yeah, thanks for having us on.

Thanks, Jordan.

Okay, so take me through it. When did you guys first discover this and what was the initial conversations about when you were getting prepped to write this article?

Yeah, so the main thing is a tip-off from this great guy on Twitter called Lithos, Lithos Coffee. Yeah, he made a great series of tweets. I'm not sure how he found the patent, but it's been there for a while actually, at least 2025, and shows like specific and a unique strategy in terms of how to integrate the strengths of ASML, but apply it to hybrid bonding. Yeah, so from there we went on and we did a bit more research into the startup SuperTrac. that is engineering this conveyor system. And then we, yeah, dug in and compared the differences. And so it's definitely, you know, not gonna be happening anytime soon, right? It's several years out, but it's at least worth discussing because it's very different to all the current tools out there.

Yes. And in fact, we started to, well, there was an advanced packaging series that Dylan and other teammates wrote back in 2023 or even earlier. So we started to focus on this area long time ago, and that's why Any news in this segment interests us.

Makes sense. So what's the high level, what's the high level difference? Maybe there's some people listening here who don't understand the hybrid bonding description or concept. Can you give the high level intro and then we can talk about the specifics?

Yeah. So yeah, I will say on a very high level, a traditional tool from the likes of Bessey and stuff for a die-to-wafer system, which is what this is going to be, is you have a static wafer. that is a base wafer, right? For example, you have a hybrid bonding, you have a top die and a bottom die. And so your base wafer will be the target and you'll have a pick and place machine that will take the chiplets for the top die and sort of align them and place them onto the base wafer to make sure that they're all properly aligned. And so that is the main tool that we're talking about here. Before that, there's several preparation steps and measurement steps to make sure that everything is aligned. And after that, there's also other steps of hybrid bonding, such as annealing and processing. So those will not be covered here, but the main one is this pick and place tool. And what ASML is doing differently with this pattern is trying to integrate some of the metrology features into a conveyor belt system. So instead of the dies being pick and placed onto a wafer, now you have the dies going around the carousel on this track that you see here, going through the various stations in each section, right, for measurement and for plasma activation, right? And then finally gone down to the bonding station where the wafer in fact comes up towards the die and meets the die at the carousel. And that's where the bonding happens, right? And this, in this specific method, right, ASML is able to use several of their competencies in terms of measurement metrology as well as wafer stage handling. Right. So they are moving the wafer towards the die rather than the die towards the wafer. So that's the main difference here.

Makes sense. So you speculate that they could be building a wafer-to-wafer hybrid bonding tool as well. Can you maybe describe the difference between die-to-wafer versus wafer-to-wafer?

Yixia, you want to take that?

Sure. So the difference that the wafer-to-wafer is basically to bond 2 wafers together, whereas the die-to-wafer, as Howie described, is that we'll first Have a die and then put the die on the wafer. And die-to-wafer is more challenging compared to wafer-to-wafer because, well, it's just, it's basically there's higher requirement on the alignment. And also right now the mature tools, or we are lacking mature tools that can meet both the accuracy and also the throughput that we need. So. That's why I like, so based on the patent filings, well, there are reasons for us to believe that ASML is building both, but there are more patents about die-to-wafer that they are building. And we believe normally for ASML to enter any market, they will, as they are like their competitive positioning in the lithography, so they will aim to be the most advanced and the best. So that's why we figured that. They could be building both, but now the patent filings suggest that they are moving ahead with the die-through wafer.

Okay. So can you guys tell me a little bit about what the existing tools are? You mentioned Bessey, for example. It won't be just ASML that's building a hybrid bonding tool, right?

That's right. So the current state of the art is from the likes of Bessey and several others as well, ASMPT and such, where they're coming from a pick-and-place kind of background. So that means The businesses and what they used to do well, what they are doing very well is kind of doing the pick and place of the individual small chiplets, right? And the placement arm, the mechanical arm with the stepper motor controls and things like that, they are very good at doing the overlay, right, from the die onto the base wafer and then placing it down. It doesn't use any force, it just places it down onto the bond pads. And then the bonding step comes later when you do the anneal. Right. So that is where the current technology and state of the art is. However, ASML is coming from a different location, which is coming from the front end, right? So that means ASML's tools, they are regularly used in the sub-nanometer alignment overlay, right? When you're trying to manufacture really intricate transistors, your lithography patterning, we're looking at extremely fine grain control, right? So. It's easily order of magnitude higher precision, right? And so for ASML's perspective, it's like, okay, if we already have this, why not find a way to implement that for hybrid bonding, especially now hybrid bonding is getting to finer and finer pitches, right, for your bond, hybrid bond pitch, right? So how many signals can you get per square millimeter down and in between the 2 dies is becoming more and more important. And so by coming at it from the front-end perspective, they don't have any issues with regards to overlay. Right. Their challenge is how do we implement our capabilities or their capabilities into a system where you can bring the dies to the wafer, or in this case, the wafer to the die. Yeah. So it's a pretty novel solution, right? And we also discuss some of the challenges that they might face versus the current technologies.

Yeah. So let me take a step back. You guys mentioned this article at the beginning, right? This was February 2024. So Coming up on 3 years ago. And in the description, you know, of this article mentioning what exactly is hybrid bonding, talking through AMD 3D V-Cache. Obviously now if I go back to the present day, there's a claim in here that HBM will not adopt die-to-wafer hybrid bonding before 2029, if at all. Can you talk about like the implications of hybrid bonding, where you think it's gonna fit in, maybe? Yeah. The reasoning why?

Yeah. I would say the primary purpose of hybrid bonding is for logic, right? So because it allows you to sort of partition the IP, all your different functional units into 2 separate layers. And as you know, right, putting signal wires between these 2 units, right, to communicate between them, it's much shorter distance if you place them above each other, right? And you can connect many more wires. Whereas if you place them next to each other, you'll have some kind of limit on your data fabric. Right? How quickly or how efficiently one segment can talk to another. So actually, I have an example right here. So this is the Huawei C2 phone and inside is the 9050 chip. And it's the first chip to use, first mobile phone to use hybrid bonding and 2 separate wafers, 2 layers, right? In order to split the IP and get the most out of the process technology that they have. Case in point again is for logic, for power efficiency. And for increasing the effective area budget in a limited size, like a phone, right? So that is like the main use case we see so far. Whereas on the memory side, right, and the claims about hybrid bonding used for HBM, those are primarily for packaging reasons. Means like how many layers of memory can I stack into a given maximum thickness, right? Because all silicon has a maximum thickness of 775 microns. Right. So slightly less than 1 millimeter and people want more and more capacity, right? So if I have hybrid bonded, maybe I can have 50% higher gigabytes per HBM stack, right? On the, on the best case scenario. And so memory vendors have been, you know, putting a lot of R&D and a lot of marketing into hybrid bonding. But the ROI isn't there because fundamentally hybrid bonding is a much more expensive process to implement, right? Versus traditional reflow or thermal compression bonding, TCB, which is what they're currently using for HBM. Right. Right. So there's a small benefit to thermal performance. There's a small benefit to perhaps signal integrity. However, the main thing is just to get the density up. And right now that is not the priority of most AI labs and most requests, right? People are like, we have been asking and the memory vendors have received a lot of requests to actually reduce the number of layers for given performance and bandwidth, right? So this is currently pushing back like the the need for that many layers, right? And so if you don't have to use hybrid bonding, then you shouldn't, right? And that's why we are also making the claim where it's not gonna come anytime soon in any high-volume HBM. Mostly it'll be for logic.

Sherry, you agree with all that? Does that make sense?

Yeah, I think what Haoyi mentioned, and also in fact, we have written up a detailed article about the HBM, like the spec or the— so on that we have Run through the economics about whether it makes sense to continue to stack more or for the time being use what we have right now, the full height. So I think if you read through that, yeah, you also get more color on why, like right now, or there's a delay about the HBM. And on top of it, I think just now we've mentioned about die-to-wafer hybrid bonding being more challenging in terms of the accuracy they need and the throughput. So all these factors combined lead to the delay that we are, we believe is, will happen. And that's why our timeline for the adoption will be 2029 or beyond.

Yeah, this is quite a big difference. It's not like all adoption of new tools in the fabs comes quickly or on time in the past, but just looking at this ASML roadmap, which was published in 2024 that you guys cite in the article. There's a lot of hybrid, hybrid, hybrid, hybrid, hybrid across NAND and DRAM. Um, you know.

And of course, ASML likes to, you know, it's in their best interest to, to, um, you know, have an optimistic, uh, prediction of like the technology implementation because you want to sell more tools, uh, you want extra complexity, right? They were famously, I remember very famously, uh, they had a transistor density metric and a graph showing like a high NA adoption and the density numbers were like totally off the walls, right? Like. 300, 400, 500 million transistors per square millimeter, which is nowhere near what we even have even to this day. So yeah, uh, we'll take those with a pinch of salt.

Yeah. Makes sense. Okay. So maybe we can dig into talking about the actual tool itself, like what's super unique about it. I can start by throwing the, uh, the patent diagram that you guys annotated back on screen. Maybe you can talk through a little bit of this.

Uh, well, I'll start, but then I'll let Howie continue because I think I still remember the day when we were looking at the graph and then Howie were describing to us how The track like runs through and how, and also there's an important part of the ecosystem change that needed that I'll let Haoyi review. But what is really unique is that normally what we see or what we have on the market right now are chamber tools, which means the tools, they don't move. And it's the dies that move to different stations and get But if, yeah, as you pointed out here, the unique thing about this tool is that, well, when we read the filings, the patents, and what SML drew is that it should be running on a track, and they have named SuperTrac Conveyance, which is a company or a potential supplier for them to provide the track. And then the fundamental difference, as we pointed out, is that For BESI type of tool, the die is prepared elsewhere and like the bond head picks up the tool and then put them to the stations and for the final placement. But in ASML's design, it's that the dies sits on its own holder and then it leaves the carrier, like it stays there, move through different stations, and also only leaves until the bonding step. And yeah, I'll let Howie describe the other parts of the track and other tools that potentially could be interesting or could be challenging.

Yep. So, so again, the super interesting part here is that you, the die is not moving from the conveyor belt. So the die is always staying on the conveyor belt and it's not moving, right? Like however the die comes onto the carrier, when it's placed on the carrier, it doesn't really matter too much because then you have the different subsequent stations that will kind of measure Okay, this is how the die is oriented on the carrier, and then you'll make a subsequent compensation when you come to the bonding step later, right? But the main, the main difference here is that each of the tool functionality, each so-called chamber, has to physically come down and approach the die, right? Even down to the bonding step where the wafer has to come and approach the die that is on the carrier. So everything has to come to the die. the die in question, right? The small little chiplets. And so how do you design a system, right, where your, let's say your normal metrology, your measurement tools, right, now needs to be in a moving scenario, right? Where it has to come down to engage with the die, right? And the conveyor system. And so this is going to be pretty interesting to see how they're going to implement. And because of the non-standard form factor, right? Yeah. at least some kind of co-design agreements with several companies who do the pre-pumping phase in order for them to integrate their functionality into this track system. Of course, the other matter is that ASML could do everything themselves, which they could, in terms of especially in the metrology side, it shouldn't have a problem. But again, the challenge is how do you maintain the measurement accuracy when the tools itself starts moving, moving to come and approach the die, right? So that's going to be a big, a big question. Another one is like, how do you maintain cleanliness over such a huge surface area, right? Imagine your current tools, right? Although this is not like a front-end transistor formation kind of cleanroom, not to that level of cleanliness, but even so, right? How do you make sure that when the die moves from the, to the different stations, this track, we were talking about several meters. Right? Several square meters of area that, you know, can be exposed, right? So how they're going to contain it between when the die is moving between the tools and when the chamber comes down to approach the die, how does it handle the environment, like the air and the environment? That's one of the very interesting questions. Yeah.

Yeah. And the critical thing you guys pointed out in the article is that a single particle between 2 wafers can unbond the area and result in a defective bond. So you specify alignment accuracy and then cleanliness. Can you distinguish the 2 of those and how they might both come into play? And then maybe later we can talk about why ASML is set to benefit because they have a bit of experience keeping things clean so far.

Yep. So the 2 major things, right? So alignment, alignment is, right, you have to measure where the bond pads are relative to Where you expected them to be, and then make the relevant changes in terms of the positioning. When you come down, the wafer approaches the die, you want it to compensate for any kind of deviations, not just in the XY position, also rotational axis, and even some stuff that is out of plane. So it means the die might be slightly tilted to one side, to one angle. So, so, you know, talking about 6 degrees of freedom in terms of— how the die can be aligned. So again, that comes under the purview of like having structures on the die that you can measure. So, you know, okay, the die is in this specific orientation on the carrier, on the conveyor belt. And then on the wafer, what is the, between the scribe lines of my, of all the different dies on the wafer, what is the position of that relative to Like 3D space. And so when you come combine, when you, when you bring the 2 dies together, you have to make sure that they come vertically and they come aligned on the XY especially, right? So that is the main goal of alignment accuracy, right? So it's like the overlay and then you can approach down and contact the 2 surfaces together. Second one is on planar. So again, because hybrid bonding requires extremely flat surfaces. Okay. Right. And it has to be free of particles because the nature of the bonding is the oxide bonding from the dielectric, right? And then the anneal later where it gets heated, right? And baked. And then the copper expansion fills the void, fills the remaining gap. So if you have any kind of particles in between, right, it'll not just affect that one bond that is in the area, but because silicon is, it will lift up and cause a defect across the whole area. So it's almost like a— Right. You're, you know, when you have some kind of impurity, right, it's like forming a wedge where, you know, the whole surface cannot bond properly because there's something in the way. So, you know, making sure that when, when it's clean at one station, right, by the time it arrives at the next station, that you guarantee that it's still clean, that's a very important part.

Also, so these 2, as in the alignment, the accuracy and cleanliness, they basically, they determine the bonding yield, which is very important because ultimately when we use the tool, we want them to have good yield and then to be able to generate good throughput. So that's why these challen— or the high requirements also make hybrid bonding almost a front-end process. And that's why we are also seeing more and more front-end toolmakers. Now it's not just TML, and because hybrid bonding matters, as in it's both globally, but also matters more for China since now they are leveraging hybrid bonding. Or advanced packaging to shrink the, like shrink alternatively. So we're also seeing major Chinese semicaps, they are moving to the hybrid bonding or growing their advanced packaging tool capabilities like Nora, AMEC. They have all made moves by acquiring or basically investing to build the tool capability.

Can you explain that a little bit more? What do you mean when you say that? Hybrid bonding can take the place of shrinking logic nodes. Like you don't need high-NA tools or EUV if you're— here, how he's holding up the Huawei phone again. If you're going to build a phone like that, right? If you have hybrid bonding, you can still just make it perform better.

Yeah. So main thing is that given their limitations on process technology, right? What's available to them? How do you maximize performance? How do you keep increasing performance? Performance per watt. And so, you know, very easy way to do that, like It's just to make the die bigger, right? Use more silicon, run it at a lower voltage, lower power. That's a very naive way to look at it, but it will help to increase your power efficiency if you have more silicon available for your use. And then hybrid bonding is like a better version of that because the 2 layers of silicon, they are right next to each other, right? And you have a lot of wires connecting them. So because of the limitations that they have in terms of what kind of process technology they can apply, right? So this Hybrid bonding and this advanced packaging is sort of like another avenue for them to continue scaling. And that's why there's a lot of demand in China.

Okay. So maybe a little bit more on the technical side. Why, why exactly do you think hybrid bonding allows them to improve performance per watt or performance per millimeter squared?

Yep. So a key example that Huawei has given, and we do see it in this phone as well, is that you're able to sort of split Certain components, certain functional units within the core, for example, things that require high speed, right? You can actually place them closer together. And so there's less timing delays, there's less congestion required when these units communicate with each other. And why they're able to be put closer is because other non-critical stuff, like let's say your SRAM, your memory cells, you place them on the bottom die, right? A different layer. And so they're out of the way. And so the important stuff are closer together. Right. And then that allows them to, for example, improve the clock speed, right? They get from now up to 2.7 GHz, right? So higher clock speed without increasing the voltage or the power, right? So in, but in a general sense, right? In a naive sense, right? Just having more silicon, more area budget for a given power envelope, usually for, and also the same architecture, usually nets you slightly higher power efficiency, right? Just because— by running more silicon at a lower voltage, right? Lower voltage means there's less leakage, right? So that means less power is being wasted to transmit the signals from one end to the other. So this is why hybrid bonding helps a lot in this sense.

Makes sense. Okay. And then maybe Sherry, can you explain a little bit about the implications on China that you're referring to there? Does this imply that a hybrid bonding tool would not be subject to export controls, or does it imply that you think it's Within the scope of what a Chinese toolmaker would be able to produce for themselves?

So right now what we have seen, as in we've also mentioned in the article, is that Bessey is the leader in the die-to-wafer. And then wafer-to-wafer, we have more players like EVG, SMPT, and, but still it's mostly the international incumbents that are dominant in this field for now. But we are seeing that China or major Chinese semicaps are growing their capabilities. And we believe it's the same as in for other tools, as in there are geopolitical complexities that could drive the need or the motivation to grow the, like, as in in the homemade tools. So that's why they are, as in China is always motivated to build the own, like their own supply chain. So that is why we are seeing this. More and more initiatives by Chinese toolmakers to grow this.

Yeah. And you can see in the roadmaps as well, right? How aggressive they are in terms of implementing hybrid bonding. In, in like, for example, you just look at the data center side, right? They're working very hard to overcome the kind of power density limitations, right? So in order for them to implement hybrid bonding, and they want like a full, you know, they call logic folding, this full hybrid bonded design for the data center. Accelerators by 2030, right? And we're talking about much higher densities compared to like TSMC's SYC bond pitch-wise. So we're looking at, you know, for the kind of demand that they want, right? Especially given their process limitations, right? Also looking at, you know, even like this currently 2 layers, but even 3 layers, right? Also by 2030, right? That will, you know, reduce the yield further. Like that just means you need more tools for the same Yielded output, right? And so there's a lot of demand in that sense.

Okay. And something that you guys mentioned in passing in the article that caught my eye that I thought was interesting was the comments about the joint initiatives between ASML and TSMC, IFS, and Samsung for moving from 6-inch to 12-inch photomasks for high-NA EUV tools. Can you give me the high level and the implications there? Because that's also something that's not coming. Soon, let's say, but would allow for similar improvements, I guess, of being able to increase die size and things like that?

Yeah. So, so the main limitation of High-NA is that your reticle size is half, right? Because of the way of the anamorphic lens that is squeezing the mask pattern, squeezing it 8 ways, 8 times in one dimension, but only 4 times in another dimension. So you'll end up having the die size of maximum of like around 400 square millimeters versus currently it's 850. So in order for designers to have like a full reticle size, right, you either do a kind of a modified stitching, right, where you have a certain, you know, IMEC talk about this, ASML talk about this, where you have a so-called delineated in your floor plan, in your chip design, a specific region where, okay, I know there's going to be some kind of stitching here where I either use other layers to do the stitching, other non-high, non-high NA layers. to do the stitching, or I dedicate a certain specific area to stitch, right? So this is what's going to happen in the interim. And then in 2020 timeframe, we're looking at this 6 by 12 mask. So that just means that the mask is now double the dimension, right? Double the length in one dimension. And so when it squeezes 8 times and 4 times in the other direction, you get back the full reticle, right? And so that, you know, eases a lot of the headaches. And Also, the main thing is that it improves the throughput even more, right? So SML has talked about this high productivity tools. And so this is an extension of that where you get the full mask size, but on the high end. And so, you know, it frees up the design again, right? And then you can have higher throughput of the full reticle.

And a little bit on the, one is on the ecosystem side. This also has implications for the entire ecosystem because it's not just SML that's changing or the mask makers, but it's The entire supply chain. So that's why we also need the time, or actually for ASML, they also took time to, to work with the fabs to initiate this because of the complexities for the supply chain. And also just now, a second point that Howie touched on is about the throughput. And this is very important for ASML because management also just mentioned in recent earnings call that Their pricing is basically a value-based pricing, which means that as they increase the throughput, that's also driving up the pricing. So longer term, that's also going to be beneficial for them.

Interesting. Makes sense. Can you dig in one layer deeper on what are the supply chain implications on some of this? Like maybe you guys covered it in the research and we shouldn't talk about it now, and in that case, excuse the question, but maybe if that's not the case, then high level, like What technically is changing in the supply chain that you think would have implications?

The main thing is the entire mask inspection, production, and sort of like protection, right, with the pellicles. All of that needs to be updated to fit this larger 6 by 12, right? So, so a little fun fact, right? It's not actually 12 inches. It's like 11.2 inches or something like that in order for the mask blank to fit in the current, let's say like your FUPs. Your overhead material handling robots, right? So, but it's still enough to fit the larger mask pattern. So that's just one example. So like all your carriers, how do you carry the mask? Then your pellicles. Then if you have a double size mask area, then all your e-beam metrology inspection, mask repair, right? It's going to be even more complex, right? And so the whole industry needs to basically all agree on like, you know, how are we going to approach this larger mask size? It's very akin to wafers going from 8-inch to 12-inch. Back in the early 2000s, early 2000s. So yeah, we're looking at that kind of whole industry needs to move together to shift, and that's why you need this kind of early commitment from all the foundries and ASML to ensure that you know everyone is coming up to speed in the supply chain.

It does make me think that a little bit of what you were talking earlier, where China could be more aggressive going for hybrid bonding and build an ecosystem around that, could create even more of a split where ASML and The founders that run their tools end up just pushing further on high NA and make some decisions there. But then you mentioned that you get the reticle size back. And I'm wondering if somehow they wrap around to the same thing for chip designers where designs that are used on one can now be actually more transferable to another stack of tools in some way. But I assume that's probably not the case. Anyway, give me your high-level reaction to that. Do you think that there, we should expect with more export controls and all the geopolitics at play that there's going to be effectively 2 separate tool stacks that you build a fab on going forward? There's going to be one side pushing on hybrid bonding and the other side pushing on larger photomasks and continue to shrink everything.

So I already said that that is already happening on the EDA side, the chip design side, right? Again, because the way you design a chip with multiple layers and how you partition which block should go where, right? This is something that everyone else hasn't really had to deal with. But China is pushing very hard on this. So Huawei has teamed up with several design companies to integrate and sort of do the partitioning for the different functional groups. On everyone else's part, AMD is the original user of this SOIC hybrid bonding, but their partitioning is a lot more simple. It's just looking at the L3 caches, SRAM, And then also the so-called, like, the split line of the different layers is very distinct, right? So the CPU cores go on this layer, the memory goes on another layer, right? But whereas in the logic folding hybrid bonding case, it's looking at, okay, within the core, I have all these little functions, little, for example, like multipliers, timing relays, buffers, you know, all the small little components that make up the core. Those are being partitioned across the 2 layers. And so this kind of very advanced design flow is already happening, this split between the current Western EDA tools that have never needed to do this in the first place. And so they, you know, started doing their own. So I can at least speak to the design side, but on the supply chain manufacturing side, I'm sure Sherry can speak a bit more.

So in terms of the supply chain, I think just now we've talked about there are multiple drivers for I think for China to be building their own supply chain or trying to accelerate as much as possible. So yeah, we're not an expert on predicting what the policies could be, but what we are seeing on the ground in China is that, well, it's also from the companies themselves that they are saying that starting from this year, the domestic sufficiency initiative used to be state-led, but now it's moving to the stage whereby it's more coordinated among the toolmakers and also the fabs themselves, as in they're working together to design, to build the tools, the semi-cap equipment or EDA, and from ground level, because what China needs could be different versus like rest of the world, given some constraints. that they have. So, and we believe that that process and this kind of effort will not be affected with the policies, as in export controls. In fact, if there are export controls, as we have seen in China's semi-cap localization rate in the past few years, the export controls could accelerate or push them or increase the motivation to, to, to work harder on that. So that's what we are seeing right now.

Makes sense, guys. Okay. I am roughly out of questions. Maybe the only thing that jumps to mind as being left is the question of what's left for ASML to prove as they go through this development of the hybrid bonding tool. But we know you kept that behind the paywall, so we will skip it for now and say anybody interested in answering that question should subscribe to the research, check out the wafer fab equipment model, and yeah, reach out and let us know if you have any comments about this. So, uh, yeah, any final thoughts before we wrap up here, guys?

Yeah, just, uh, look forward to our teardown of this. Yeah.

Teardown of the Huawei phone. Let's go. We published, uh, some good stuff previously on both of those Intel and Huawei process, which is awesome. Sherry, anything from you?

I think it's always great to, to be able to work with great colleagues like Howie and also Jordan yourself, because every day I feel like the learning curve is 90 degrees here, so I hope that our readers also enjoy the, especially the technical part of our research. And yeah, we will do more and update you again on SML or other parts of the supply chain.

Awesome. Nice job, guys. Thanks for joining today.